Publications

2024

1. IEDM 2024

   Comprehensive Performance Re-Assessment of Hafnia-Based Cross-Point FeRAM with Ultra-Fast and Low-Power Operation from Device/Array Perspective

   Shengjie Cao^*, Zhiyuan Fu^*, Minyue Deng, Hao Zheng, Qianqian Huang , and Ru Huang

   In 2024 IEEE International Electron Devices Meeting (IEDM), 2024

   Abs DOI Bib

   In this work, hafnia-based selector-less cross-point FeRAM (XP-FeRAM) with ultra-fast and low-power operation is experimentally demonstrated from device-level optimization to array-level evaluation for embedded and standalone memories. For device optimization, the impacts of ferroelectric (FE) layer deposition process sequence considering different applications are investigated for the first time with the awareness of switching speed. Optimized devices show the outstanding comprehensive performance with 1.5ns switching, 2Pr of 47μC/cm2 and excellent disturbance immunity under 1.6V low-voltage operation, alone with the good reliability of extrapolated 1014 endurance cycles and 10 years data retention in scaled devices. Moreover, from array perspective, a modified V/2 operation scheme with in-situ write-back is further proposed and experimentally demonstrated in the fabricated XP-FeRAM array, resulting in the even faster operation and lower power consumption than 1T1C FeRAM. Additionally, based on the established parasitic circuit model, memory performances and scalability design spaces are robustly evaluated, showing the great potential of XP-FeRAMs for high-speed, high-density and low-power memory applications.

   @inproceedings{cao2024comprehensive,
     title = {Comprehensive Performance Re-Assessment of Hafnia-Based Cross-Point FeRAM with Ultra-Fast and Low-Power Operation from Device/Array Perspective},
     author = {Cao, Shengjie and Fu, Zhiyuan and Deng, Minyue and Zheng, Hao and Huang, Qianqian and Huang, Ru},
     booktitle = {2024 IEEE International Electron Devices Meeting (IEDM)},
     pages = {1--4},
     year = {2024},
     organization = {IEEE},
     doi = {10.1109/IEDM50854.2024.10873447}
   }

2. IEEE TED 2024

   Hafnia-Based High-Disturbance-Immune and Selector-Free Cross-Point FeRAM

   Zhiyuan Fu, Shengjie Cao, Hao Zheng, Jin Luo, Qianqian Huang , and Ru Huang

   IEEE Transactions on Electron Devices, 2024

   Abs DOI Bib

   This study presents an experimental demonstration of 3-D-stackable hafnia-based selector-free cross-point FeRAM, with enhanced disturbance immunity achieved through design technology co-optimization (DTCO). Considering ferroelectric (FE) dynamics, the disturbance behavior of FE devices has been systematically and quantitatively examined using the proposed “pulse-disturb” analysis method. Through the optimization of grain uniformity and interfacial layers, the fabricated Hf0.5Zr0.5O2 (HZO) FE capacitor exhibits large grain size exceeding 30 nm with record best disturbance immunity among FE-HZO. It also achieves a significant improvement of MW in selector-free FeRAM operation and enhanced remnant polarization ( Pr ) of approximately 23 μC/cm2, low operation voltage (2.4 V), high endurance (1013 cycles), long retention capability (ten years), and excellent potential for 3-D stacking. Moreover, to address the multiple pulses disturb issue, a novel “disturb-recovery” pulsing method is proposed, showing multidisturb-free operation for practical cross-point array applications. Based on the above strategies, 1-kbit selector-free cross-point FeRAM array is experimentally demonstrated with successful read/write operation, indicating its great potential for high-density and low-power memory applications.

   @article{fu2024hafnia,
     title = {Hafnia-Based High-Disturbance-Immune and Selector-Free Cross-Point FeRAM},
     author = {Fu, Zhiyuan and Cao, Shengjie and Zheng, Hao and Luo, Jin and Huang, Qianqian and Huang, Ru},
     journal = {IEEE Transactions on Electron Devices},
     year = {2024},
     publisher = {IEEE},
     doi = {10.1109/TED.2024.3369569}
   }

2023

1. IEDM 2023

   First demonstration of hafnia-based selector-free FeRAM with high disturb immunity through design technology co-optimization

   Zhiyuan Fu^*, Shengjie Cao^*, Hao Zheng, Jin Luo, Qianqian Huang , and Ru Huang

   In 2023 International Electron Devices Meeting (IEDM), 2023

   Abs DOI Bib

   In this work, 3D-stackable hafnia-based selector-free FeRAM is experimentally demonstrated for the first time, showing significantly improved disturb immunity through design technology co-optimization. With ferroelectric (FE) dynamics considered, based on the proposed pulse-disturb analysis method for FE capacitors, the disturb behavior of FE-based cross-point arrays has been systematically and quantitatively investigated. By grain uniformity and interfacial layer optimization, the fabricated optimized Hf0.5Zr0.5O2 (HZO) FE capacitor shows the record best disturb immunity among FE-HZO and 71.3% of MW improvement for FeRAM operation due to the large grain size (>30nm), along with the advantages of enhanced remnant polarization (Pr) ( 23 μC/cm2), low operation voltage (2.4V), high endurance (1013 cycles), long retention (10 years) and excellent 3D-stackable potential. Moreover, to address the multiple pulses disturb issue, a new disturb-recovery pulsing method is further proposed, showing multi-disturb-free operation for practical cross-point array applications. Based on the above strategies, the first 1 kbit cross-point array for selector-free FeRAM based on the optimized HZO devices is experimentally demonstrated with successful read/write operation, indicating its great potential for high-density and low-power memory applications.

   @inproceedings{fu2023first,
     title = {First demonstration of hafnia-based selector-free FeRAM with high disturb immunity through design technology co-optimization},
     author = {Fu, Zhiyuan and Cao, Shengjie and Zheng, Hao and Luo, Jin and Huang, Qianqian and Huang, Ru},
     booktitle = {2023 International Electron Devices Meeting (IEDM)},
     pages = {1--4},
     year = {2023},
     organization = {IEEE},
     doi = {10.1109/IEDM45741.2023.10413887}
   }

2021

1. IEEE TVLSI 2021

   DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays

   Hongtao Zhong^*, Shengjie Cao^*, Li Jiang, Xia An, Vijaykrishnan Narayanan, Yongpan Liu, Huazhong Yang, and Xueqing Li

   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov 2021

   Abs DOI Bib

   Ternary content addressable memory (TCAM) is one type of associative memory and has been widely used in caches, routers, and many other mapping-aware applications. While the conventional SRAM-based TCAM is high speed and bulky, there have been denser but slower and less reliable nonvolatile TCAMs using nonvolatile memory (NVM) devices. Meanwhile, some CMOS TCAMs using dynamic memories have been also proposed. Although dynamic TCAM could be denser than the 16T SRAM TCAM and more reliable than the nonvolatile TCAMs, CMOS dynamic TCAMs still suffer from the row-by-row refresh energy and time overheads. In this article, we propose dynamic TCAM using nanoelectromechanical (NEM) relays (DyTAN), and utilize one-shot refresh (OSR) to solve the memory refresh problem. By exploiting the unique NEM relay characteristics, DyTAN outperforms the existing works in the balance between density, speed, and power efficiency. Compared with the 16T SRAM-based TCAM, the 5T CMOS dynamic TCAM, the 2T2R TCAM, and the 2FeFET TCAM, evaluations show that the proposed DyTAN reduces the write energy by up to 2.3\times , 1.3\times , 131\times , and 13.5\times , and improves the search energy-delay-product (EDP) by up to 12.7\times , 1.7\times , 1.3\times , and 2.8\times , respectively.

   @article{9570131,
     author = {Zhong, Hongtao and Cao, Shengjie and Jiang, Li and An, Xia and Narayanan, Vijaykrishnan and Liu, Yongpan and Yang, Huazhong and Li, Xueqing},
     journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
     title = {DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays},
     year = {2021},
     volume = {29},
     number = {11},
     pages = {1981-1993},
     keywords = {Relays;Nanoelectromechanical systems;Nonvolatile memory;Logic gates;FeFETs;Electrodes;Very large scale integration;Dynamic ternary content addressable memory (TCAM);low power;(snanoelectromechanical (NEM) relay;TCAM},
     doi = {10.1109/TVLSI.2021.3115622},
     issn = {1557-9999},
     month = nov
   }

2. DATE 2021

   Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays

   Hongtao Zhong^*, Shengjie Cao^*, Huazhong Yang, and Xueqing Li

   In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Feb 2021

   Abs DOI Bib

   Ternary content addressable memory (TCAM) has been a critical component in caches, routers, etc., in which density, speed, power efficiency, and reliability are the major design targets. There have been the conventional low-write-power but bulky SRAM-based TCAM design, and also denser but less reliable or higher-write-power TCAM designs using nonvolatile memory (NVM) devices. Meanwhile, some TCAM designs using dynamic memories have been also proposed. Although dynamic design TCAM is denser than CMOS SRAM TCAM and more reliable than NVM TCAM, the conventional row-by-row refresh operations land up with a bottleneck of interference with normal TCAM activities. Therefore, this paper proposes a custom low-power dynamic TCAM using nanoelectromechanical (NEM) relay devices utilizing one-shot refresh to solve the memory refresh problem. By harnessing the unique NEM relay characteristics with a proposed novel cell structure, the proposed TCAM occupies a small footprint of only 3 transistors (with two NEM relays integrated on the top through the back-end-of-line process), which significantly outperforms the density of 16-transistor SRAM-based TCAM. In addition, evaluations show that the proposed TCAM improves the write energy efficiency by 2.31x, 131x, and 13.5x over SRAM, RRAM, and FeFET TCAMs, respectively; The search energy-delay-product is improved by 12.7x, 1.30x, and 2.83x over SRAM, RRAM, and FeFET TCAMs, respectively.

   @inproceedings{9474177,
     author = {Zhong, Hongtao and Cao, Shengjie and Yang, Huazhong and Li, Xueqing},
     booktitle = {2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
     title = {Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays},
     year = {2021},
     volume = {},
     number = {},
     pages = {1100-1103},
     keywords = {Associative memory;Nanoelectromechanical systems;Nonvolatile memory;Random access memory;Benchmark testing;Reliability engineering;Nanoscale devices;Ternary content addressable memory (TCAM);low-power;NEM relay;beyond-CMOS;dynamic memory},
     doi = {10.23919/DATE51398.2021.9474177},
     issn = {1558-1101},
     month = feb
   }